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ltc1661 1 1661fa block diagram features description micropower dual 10-bit dac in msop the ltc ? 1661 integrates two accurate, serially address - able, 10-bit digital-to-analog converters (dacs) in a single tiny ms8 package. each buffered dac draws just 60a total supply current, yet is capable of supplying dc output currents in excess of 5ma and reliably driving capacitive loads up to 1000pf. sleep mode further reduces total supply current to a negligible 1a. linear technologys proprietary, inherently monotonic voltage interpolation architecture provides excellent lin - earity while allowing for an exceptionally small external form factor. the double-buffered input logic provides simultaneous update capability and can be used to write to either dac without interrupting sleep mode. ultralow supply current, power-saving sleep mode and extremely compact size make the ltc1661 ideal for battery-powered applications, while its straightforward usability, high performance and wide supply range make it an excellent choice as a general purpose converter. for additional outputs and even greater board density, please refer to the ltc1660 micropower octal dac for 10 - bit applications. for 8-bit applications, please consult the ltc1665 micropower octal dac. differential nonlinearity (dnl) applications n tiny: two 10-bit dacs in an 8-lead msop half the board space of an so-8 n micropower: 60a per dac sleep mode: 1a for extended battery life n rail-to-rail voltage outputs drive 1000pf n wide 2.7v to 5.5v supply range n double buffered for independent or simultaneous dac updates n reference range includes supply for ratiometric 0v-to-v cc output n reference input has constant impedance over all codes (260k typ)eliminates external buffers n 3-wire serial interface with schmitt trigger inputs n differential nonlinearity: ?0.75lsb max n mobile communications n digitally controlled amplifiers and attenuators n portable battery-powered instruments n automatic calibration for manufacturing n remote industrial devices l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. cs/ld 1661 bd 1 4 10-bit dac a 10-bit dac b address decoder control logic shift register sck 2 d in ref 3 v out a 8 5 gnd 7 v cc v out b 6 latch latch latch latch code 0 256 512 768 1023 lsb 1661 g02 0.75 ?0.75 0.60 0.40 0.20 0 ?0.20 ?0.40 ?0.60
ltc1661 2 1661fa absolute maximum ratings v cc to gnd .............................................. C0.3v to 7.5v logic inputs to gnd ............................... C0.3v to 7.5v v out a , v out b , ref to gnd ........... C0.3v to v cc + 0.3v maximum junction temperature ........................... 125c storage temperature range .................. C65c to 150c (note 1) 1 2 3 4 cs/ld sck d in ref 8 7 6 5 v out a gnd v cc v out b top view ms8 package 8-lead plastic msop t jmax = 125c, ja = 150c/w 1 2 3 4 8 7 6 5 top view cs/ld sck d in ref v out a gnd v cc v out b n8 package 8-lead plastic dip t jmax = 150c, ja = 100c/w pin configuration electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v ref v cc , v out unloaded unless otherwise noted. order information lead free finish tape and reel part marking package description temperature range ltc1661cms8#pbf ltc1661cms8#trpbf ltdv 8-lead plastic msop 0c to 70c ltc1661ims8#pbf ltc1661ims8#trpbf ltdw 8-lead plastic msop C40c to 85c ltc1661cn8#pbf ltc1661cn8#trpbf ltc1661cn8 8-lead plastic dip 0c to 70c ltc1661in8#pbf ltc1661in8#trpbf ltc1661in8 8-lead plastic dip C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ operating temperature range ltc1661c ............................................... 0c to 70c ltc1661i ............................................ C40c to 85c lead temperature (soldering, 10 sec) ................. 300c symbol parameter conditions min typ max units accuracy resolution l 10 bits monotonicity 1v v ref v cc C 0.1v (note 2) l 10 bits dnl differential nonlinearity 1v v ref v cc C 0.1v (note 2) l 0.1 0.75 lsb inl integral nonlinearity 1v v ref v cc C 0.1v (note 2) l 0.4 2 lsb v os offset error measured at code 20 l 5 30 mv v os temperature coefficient 15 v/c fse full-scale error v cc = 5v, v ref = 4.096v l 1 12 lsb full-scale error temperature coefficient 30 v/c psr power supply rejection v ref = 2.5v 0.18 lsb/v
ltc1661 3 1661fa electrical characteristics timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v ref v cc , v out unloaded unless otherwise noted. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. symbol parameter conditions min typ max units reference input input voltage range l 0 v cc v resistance active mode l 140 260 k capacitance l 15 pf i ref reference current sleep mode l 0.001 1 a power supply v cc positive supply voltage for specified performance l 2.7 5.5 v i cc supply current v cc = 5v (note 3) v cc = 5v (note 3) sleep mode (note 3) l l l 120 95 1 195 154 3 a a a dc performance short-circuit current low v out = 0v, v cc = v ref = 5v, code = 1023 l 10 25 100 ma short-circuit current high v out = v cc = v ref = 5v, code = 0 l 7 19 120 ma ac performance voltage output slew rate rising (notes 4, 5) falling (notes 4, 5) 0.60 0.25 v/s v/s voltage output settling time to 0.5lsb (notes 4, 5) 30 s capacitive load driving 1000 pf digital i/o v ih digital input high voltage v cc = 2.7v to 5.5v v cc = 2.7v to 3.6v l l 2.4 2.0 v v v il digital input low voltage v cc = 4.5v to 5.5v v cc = 2.7v to 5.5v l l 0.8 0.6 v v i lk digital input leakage v in = gnd to v cc l 10 a c in digital input capacitance (note 6) l 10 pf symbol parameter conditions min typ max units v cc = 4.5v to 5.5v t 1 d in valid to sck setup l 40 ns t 2 d in valid to sck hold l 0 ns t 3 sck high time (note 6) l 30 ns t 4 sck low time (note 6) l 30 ns t 5 cs/ld pulse width (note 6) l 80 ns t 6 lsb sck high to cs/ld high (note 6) l 30 ns t 7 cs/ld low to sck high (note 6) l 20 ns t 9 sck low to cs/ld low (note 6) l 0 ns t 11 cs/ld high to sck positive edge (note 6) l 20 ns sck frequency square wave (note 6) l 16.7 mhz
ltc1661 4 1661fa timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. symbol parameter conditions min typ max units v cc = 2.7v to 5.5v t 1 d in valid to sck setup (note 6) l 60 ns t 2 d in valid to sck hold (note 6) l 0 ns t 3 sck high time (note 6) l 50 ns t 4 sck low time (note 6) l 50 ns t 5 cs/ld pulse width (note 6) l 100 ns t 6 lsb sck high to cs/ld high (note 6) l 50 ns t 7 cs/ld low to sck high (note 6) l 30 ns t 9 sck low to cs/ld low (note 6) l 0 ns t 11 cs/ld high to sck positive edge (note 6) l 30 ns sck frequency square wave (note 6) l 10 mhz note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: nonlinearity and monotonicity are defned from code 20 to code 1023 (full scale). see applications information. note 3: digital inputs at 0v or v cc . note 4: load is 10k in parallel with 100pf. note 5: v cc = v ref = 5v. dac switched between 0.1v fs and 0.9v fs , i.e., codes k = 102 and k = 922. note 6: guaranteed by design and not subject to test. timing diagram d in cs/ld sck a3 a2 1661 td a1 x1 x0 t 2 t 9 t 11 t 5 t 7 t 6 t 1 t 3 t 4
ltc1661 5 1661fa typical performance characteristics load regulation vs output current load regulation vs output current large-signal step response minimum v out vs load current (output sinking) integral nonlinearity (inl) mid-scale output voltage vs load current differential nonlinearity (dnl) mid-scale output voltage vs load current minimum supply headroom vs load current (output sourcing) code 0 256 512 768 1023 lsb 1661 g01 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 code 0 256 512 768 1023 lsb 1661 g02 0.75 ?0.75 0.60 0.40 0.20 0 ?0.20 ?0.40 ?0.60 0 2 4 6 8 10 v cc ? v out (mv) 1661 g03 1400 1200 1000 800 600 400 200 0 ?55c 25c 125c v ref = 4.096v ?v out < 1lsb code = 1023 | i out | (ma) (sourcing) | i out | (ma) (sinking) 0 2 4 6 8 10 v out (mv) 1661 g04 1400 1200 1000 800 600 400 200 0 ?55c 25c 125c v cc = 5v code = 0 i out (ma) ?30 ?20 ?10 0 10 20 30 v out (v) 1661 g05 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 v cc = 4.5v v cc = 5v v cc = 5.5v v ref = v cc code = 512 sink source i out (ma) ?15 ?4?8?12 0 4 8 12 15 v out (v) 1661 g06 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 v cc = 2.7v v cc = 3v v cc = 3.6v v ref = v cc code = 512 sink source i out (ma) ?2 ?1 0 1 2 ?v out (lsb) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 1661 g07 v cc = v ref = 5v code = 512 sink source i out (a) ?500 0 500 ?v out (lsb) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 1661 g08 sink source v cc = v ref = 3v code = 512 time (s) 0 20 40 60 80 100 v out (v) 1661 g09 5 4 3 2 1 0 v cc = v ref = 5v 10% to 90% step code = 102 code = 922
ltc1661 6 1661fa pin functions cs/ld (pin 1): serial interface chip select/load input. when cs /ld is low, sck is enabled for shifting data on d in into the register. when cs/ld is pulled high, sck is disabled and the operation(s) specified in the control code, a3-a0, is (are) performed. cmos and ttl compatible. sck (pin 2): serial interface clock input. cmos and ttl compatible. d in (pin 3): serial interface data input. input word data on the d in pin is shifted into the 16-bit register on the rising edge of sck. cmos and ttl compatible. ref (pin 4): reference voltage input. 0v v ref v cc . v out a , v out b (pin 8, pin 5): dac analog voltage outputs. the output range is 0 v outa, v outb v ref 1023 1024 ? ? ? ? ? ? v cc (pin 6): supply voltage input. 2.7v v cc 5.5v. gnd (pin 7): system ground. typical performance characteristics supply current vs logic input voltage supply current vs temperature logic input voltage (v) 0 1 2 3 4 5 supply current (ma) 1661 g10 1.0 0.8 0.6 0.4 0.2 0 all digital inputs shorted together temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 125 supply current (a) 1661 g11 150 140 130 120 110 100 90 80 70 60 50 v cc = 5.5v v ref = v cc code = 1023 v cc = 4.5v v cc = 3.6v v cc = 2.7v
ltc1661 7 1661fa definitions differential nonlinearity (dnl): the difference between the measured change and the ideal 1lsb change for any two adjacent codes. the dnl error between any two codes is calculated as follows: dnl = ? v out C lsb lsb where ?v out is the measured voltage difference between two adjacent codes. full-scale error (fse): the deviation of the actual full-scale voltage from ideal. fse includes the effects of offset and gain errors (see applications information). integral nonlinearity (inl): the deviation from a straight line passing through the endpoints of the dac transfer curve (endpoint inl). because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. the inl error at a given input code is calculated as follows: inl = v out C v os C v fs C v os ( ) code 1023 ? ? ? ? ? ? lsb where v out is the output voltage of the dac measured at the given input code. least significant bit (lsb): the ideal voltage difference between two successive codes. lsb = v ref 1024 resolution (n): defines the number of dac output states (2n) that divide the full-scale range. resolution does not imply linearity. voltage offset error (v os ): nominally, the voltage at the output when the dac is loaded with all zeros. a single supply dac can have a true negative offset, but the out - put cannot go below zero (see applications information). for this reason, single supply dac offset is measured at the lowest code that guarantees the output will be greater than zero.
ltc1661 8 1661fa operation transfer function the transfer function for the ltc1661 is: v out(deal) = k 1024 ? ? ? ? ? ? v ref where k is the decimal equivalent of the binary dac input code d9-d0 and v ref is the voltage at ref (pin 6). power-on reset the ltc1661 positively clears the outputs to zero scale when power is first applied, making system initialization consistent and repeatable. power supply sequencing the voltage at ref (pin 4) must not ever exceed the voltage at v cc (pin 6) by more than 0.3v. particular care should be taken in the power supply turn-on and turn- off sequences to assure that this limit is observed. see absolute maximum ratings. serial interface see table 1. the 16-bit input word consists of the 4-bit control code, the 10-bit input code and two dont-care bits. table 1. ltc1661 input word a3 a2 a1 control code a0 d9 d8 d7 d6 d5 d4 d3 d2 d1 x1 x0d0 input code input word don?t care after the input word is loaded into the register (see figure?1), it is internally converted from serial to parallel format. the parallel 10-bit-wide input code data path is then buffered by two latch registers. the first of these, the input register, is used for loading new input codes. the second buffer, the dac register, is used for updating the dac outputs. each dac has its own 10 - bit input register and 10-bit dac register. by selecting the appropriate 4-bit control code (see table?2) it is possible to perform single operations, such as loading one dac or changing power-down status (sleep/wake). in addition, some control codes perform two or more operations at the same time. for example, one such code loads dac a, updates both outputs and wakes the part up. the dacs can be loaded separately or together, but the outputs are always updated together. register loading sequence see figure 1. with cs /ld held low, data on the d in input is shifted into the 16-bit shift register on the positive edge of sck. the 4-bit control code, a3-a0, is loaded first, then the 10-bit input code, d9-d0, ordered msb-to-lsb in each case. two dont-care bits, x1 and x0, are loaded last. when the full 16-bit input word has been shifted in, cs/ld is pulled high, causing the system to respond according to table?2. the clock is disabled internally when cs /ld is high. note: sck must be low when cs /ld is pulled low. sleep mode dac control code 1110 b is reserved for the special sleep instruction (see table 2). in this mode, the digital parts of the circuit stay active while the analog sections are disabled; static power consumption is greatly reduced. the reference input and analog outputs are set in a high impedance state and all dac settings are retained in memory so that when sleep mode is exited, the outputs of dacs not updated by the wake command are restored to their last active state. sleep mode is initiated by performing a load sequence using control code 1110 b (the dac input code d9-d0 is ignored). to save instruction cycles, the dacs may be prepared with new input codes during sleep (control codes 0001 b and 0010 b ); then, a single command (1000 b ) can be used both to wake the part and to update the output values.
ltc1661 9 1661fa operation table 2. dac control functions control input register status dac register status power-down status (sleep/wake) comments a3 a2 a1 a0 0 0 0 0 no change no update no change no operation. power-down status unchanged (part stays in wake or sleep mode) 0 0 0 1 load dac a no update no change load input register a with data. dac outputs unchanged. power-down status unchanged 0 0 1 0 load dac b no update no change load input register b with data. dac outputs unchanged. power-down status unchanged 0 0 1 1 reserved 0 1 0 0 reserved 0 1 0 1 reserved 0 1 1 0 reserved 0 1 1 1 reserved 1 0 0 0 no change update outputs wake load both dac regs with existing contents of input regs. outputs update. part wakes up 1 0 0 1 load dac a update outputs wake load input reg a. load dac regs with new contents of input reg a and existing contents of reg b. outputs update. part wakes up 1 0 1 0 load dac b update outputs wake load input reg b. load dac regs with existing contents of input reg a and new contents of reg b. outputs update. part wakes up 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 no change no update wake part wakes up. input and dac regs unchanged. dac outputs reflect existing contents of dac regs 1 1 1 0 no change no update sleep part goes to sleep. input and dac regs unchanged. dac outputs set to high impedance state 1 1 1 1 load dacs a, b with same 10-bit code update outputs wake load both input regs. load both dac regs with new contents of input regs. outputs update. part wakes up d in sck cs/ld a3 a2 input code don?t care a1 a0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x1 x0 1661 f01 1615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (sck enabled) (ltc1661 responds) control code input word w 0 figure 1. register loading sequence
ltc1661 10 1661fa operation voltage outputs each of the rail-to-rail output amplifiers contained in the ltc1661 can typically source or sink up to 5ma (v cc ?=?5v). the outputs swing to within a few millivolts of either supply when unloaded and have an equivalent output resistance of 85 (typical) when driving a load to the rails. the output amplifiers are stable driving capacitive loads up to 1000pf. a small resistor placed in series with the output can be used to achieve stability for any load capacitance. a 1f load can be successfully driven by inserting a 20 resis - tor in series with the v out pin. a 2.2f load needs only a 10 resistor, and a 10f electrolytic capacitor can be used without any resistor (the equivalent series resistance of the capacitor itself provides the required small resistance). in any of these cases, larger values of resistance, capacitance or both may be substituted for the values given. rail-to-rail output considerations in any rail-to-rail dac, the output swing is limited to volt - ages within the supply range. if the dac offset is negative, the output for the lowest codes limits at 0v as shown in figure 2b. similarly, limiting can occur near full scale when the ref pin is tied to v cc . if v ref = v cc and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc as shown in figure 2c. no full-scale limiting can occur if v ref is less than v cc C fse. offset and linearity are defined and tested over the region of the dac transfer function where no output limiting can occur. 1661 f02 input code (2b) output voltage negative offset 0v 512 0 1023 input code output voltage (2a) v ref = v cc v ref = v cc (2c) input code output voltage positive fse figure 2. effects of rail-to-rail operation on a dac transfer curve. (2a) overall transfer function (2b) effect of negative offset for codes near zero scale (2c) effect of positive full-scale error for input codes near full scale when v ref = v cc
ltc1661 11 1661fa typical applications ? + u3a lt1368 pin driver (1 0f n) v h v l v out 1661 f03 logic drive 4 ?5v 10v 5v v h = 7.5v (from main input dac) v l = ?2.5v (from main input dac) v a1 = 2.5v v h = v h + v h v l = v l + ?v l v b1 r4 5k 0.1f 8 3 1 cs/ld d in sck 4 6 3 2 1 8 5 2 0.1f r3 50k ltc1661 u1 dac a dac b r2 50k r1 5k 0.1f + ? u3b lt1368 5v v b2 v a2 = 2.5v 6 1 4 6 3 2 7 5 8 5 0.1f r7 50k ltc1661 u2 dac b dac a r5 50k r6 5k 7 r8 5k 0.1f 0.1f for each u1 and u2 code a code b ?v h , ?v l 512 1023 ?250mv 512 512 0 512 0 250mv ?2.5v 250mv 7.5v 250mv v a2 = 2.5v v a1 = v h + (v a1 ? v b1 ) v h = r1 r2 v l + (v a2 ? v b2 ) v l = for values shown, ?v h , ?v l adjustment range = 250mv ?v h , ?v l step size = 500v r1 r2 2 0.1f v in 4.3v ltc1258-4.1 1 4.096v 4 ref d in sck cs/ld v outa gnd v cc ltc1661 v outb 0v to 4.096v (4mv/bit) t 0v to 4.096v (4mv/bit) 1661 f04 4 3 2 1 8 5 7 6 0.1f figure 3. pin driver v h and v l adjustment in ate applications figure 4. using the ltc1258 and the ltc1661 in a single li-ion battery application
ltc1661 12 1661fa package description ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev f) msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ? 0.38 (.009 ? .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ? 6 typ detail ?a? detail ?a? gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc n8 package 8-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510) n8 1002 .065 (1.651) typ .045 ? .065 (1.143 ? 1.651) .130 .005 (3.302 0.127) .020 (0.508) min .018 .003 (0.457 0.076) .120 (3.048) min .008 ? .015 (0.203 ? 0.381) .300 ? .325 (7.620 ? 8.255) .325 +.035 ?.015 +0.889 ?0.381 8.255 ( ) 1 2 3 4 8 7 6 5 .255 .015* (6.477 0.381) .400* (10.160) max note: 1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc
ltc1661 13 1661fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 11/10 removed typical values from timing characteristics section 3, 4
ltc1661 14 1661fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 1999 lt 1110 rev a ? printed in usa related parts typical application ? + u3a lt1368 pin driver (1 0f n) v h v l v out 1661 f03 logic drive 4 ?5v 10v 5v v h = 7.5v (from main input dac) v l = ?2.5v (from main input dac) v a1 = 2.5v v h = v h + v h v l = v l + ?v l v b1 r4 5k 0.1f 8 3 1 cs/ld d in sck 4 6 3 2 1 8 5 2 0.1f r3 50k ltc1661 u1 dac a dac b r2 50k r1 5k 0.1f + ? u3b lt1368 5v v b2 v a2 = 2.5v 6 1 4 6 3 2 7 5 8 5 0.1f r7 50k ltc1661 u2 dac b dac a r5 50k r6 5k 7 r8 5k 0.1f 0.1f for each u1 and u2 code a code b ?v h , ?v l 512 1023 ?250mv 512 512 0 512 0 250mv ?2.5v 250mv 7.5v 250mv v a2 = 2.5v v a1 = v h + (v a1 ? v b1 ) v h = r1 r2 v l + (v a2 ? v b2 ) v l = for values shown, ?v h , ?v l adjustment range = 250mv ?v h , ?v l step size = 500v r1 r2 pin driver v h and v l adjustment in ate applications part number description comments ltc1446/ltc1446l dual 12-bit v out dacs in so-8 package with internal reference ltc1446: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1446l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1448 dual 12-bit v out dac in so-8 package v cc = 2.7v to 5.5v, external reference can be tied to v cc ltc1454/ltc1454l dual 12-bit v out dacs in so-16 package with added functionality ltc1454: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1454l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1458/ltc1458l quad 12-bit rail-to-rail output dacs with added functionality ltc1458: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1659 single rail-to-rail 12-bit v out dac in 8-lead msop package v cc : 2.7v to 5.5v low power multiplying v out dac. output swings from gnd to ref. ref input can be tied to v cc ltc1663 single 10-bit v out dac in sot-23 package v cc = 2.7v to 5.5v, internal reference, 60a ltc1665/ltc1660 octal 8/10-bit v out dac in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output

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